The invention relates to the field of direct memory access ("DMA") and, in particular, to dynamic chaining of DMA operations.
DMA operations facilitate transference of data from a source (e.g., a memory, input/output (I/O) device, etc.) to a destination (e.g., another memory, I/O device, etc.) without requiring a host processor to control the data transfer itself. Transfers may be between like or different device types (e.g., memory-memory, memory-I/O device, etc.). In a DMA operation, the host processor initially provides information to a DMA controller (also referred to as a "Bus Master") specifying the parameters of a data-transfer operation (e.g., the address of a block of data to be transferred, the amount of such data, the destination address, etc.; referred to collectively herein as "data-transfer parameters"). The DMA controller, thereafter, handles the actual data transfer.
When performing DMA operations, the DMA controller gains control of an interconnecting bus (or busses) between the source and destination devices. The controller receives data-transfer parameters from a host processor and notifies the processor when the operation has been completed. One well-known method for conveying data-transfer parameters between a processor and DMA controller is through "channel control blocks" or "descriptors" (referred to herein as "control blocks"); i.e., data structures created by the processor, stored in a memory and accessed by the DMA controller for effecting a particular DMA operation.
To facilitate the execution of multiple DMA operations in succession, it is known to "chain" such operations together by constructing a linked list of corresponding control blocks. The linked list may be created through memory addresses; i.e., each block contains the address of the block disposed immediately subsequent in the chain. (Such memory address is referred to herein as a "link address," a "next control block pointer" or simply a "block pointer.") In conventional designs, a "chain bit" may be held in each control block to indicate whether a block currently undergoing processing is linked to a subsequent block. Under such circumstances, the host processor may be required to poll this bit to determine whether a chaining operation is to be carried out. Such polling may contribute to bus traffic in the system.
Often, while a DMA controller is performing a data transfer operation specified by a particular control block, the host processor specifies additional data transference operations by creating additional control blocks. When additional control blocks are created, it is desirable to append the new control blocks to the existing linked list of control blocks to allow the DMA controller to process all the control blocks in one uninterrupted sequence of data-transfer operations. Without the ability to append such control blocks, the DMA controller will deactivate upon completion of the data-transfer operation specified by the original linked list. Then, the host processor will need to restart the DMA controller to handle the data transfer operation specified by the new group of control blocks. Such operation of deactivating and restarting the DMA controller may result in significant time delays and should be avoided when possible.
The appending of control block(s) to an existing block (or linked-list of blocks) before a corresponding DMA operation is complete is referred to herein as dynamic chaining of DMA operations ("dynamic DMA chaining"). Linked lists of control blocks (also referred to herein as "chains" or "control-block chains") that allow such appending of additional control blocks are considered "dynamic". In contrast, chains that are defined prior to the start of a corresponding DMA operation and cannot be appended to before such operation is complete are considered "static".
The transfer of high-speed streaming data (such as audio data in DVD or CD-ROM technologies) requires frequent dynamic DMA chaining. At least one known implementation of dynamic DMA chaining, however, suffers from poor performances as the DMA controller actually suspends operations during the chaining process in order to prevent race conditions. The term "race condition" as used herein, refers to a situation where data (i.e., a control block) can be inadvertently omitted from its intended position within a given sequence of data transference operations (and thereby missed during processing) due to the timing of at least two events. Such condition may arise, for example, when a current control block in a chain is processed before new block(s), intended to be processed before the current block, can be timely inserted in the current control-block chain. Accordingly, it would be desirable to facilitate dynamic chaining of DMA operations without suspending the controller or incurring such race conditions.
In another known implementation of dynamic DMA chaining, a DMA controller must access a memory twice to fetch and update information held in a given control block at least each time dynamic DMA chaining occurs. The update is to obtain the block pointer of appended block(s) for a current block being processed. It would be further desirable to reduce or eliminate the need to provide such frequent updates of block pointers.